RTL Design of SHA3 512/256 (also known as Keccak algorithm)
Designed to offer you a hash at every clock cycle running at speeds of 550MHz
- Tested on the Xilinx Virtex UltraScale+ FPGA BCU1525 Acceleration Development Kit
- Connected with PCIe Interface Host for sending/receiving data
- Designing custom mining software (multi-threaded) in Python to communicate to mining pool with Stratum protocol
- Benchmarked on mining pools with 17GH/s
- Optimized for throughput
- RTL Design of SHA-256 (aka Bitcoin algorithm)
Designed to give you a hash at every single clock cycle running at 350MHz
- Tested on the BCU1525 Acceleration Development Kit with PCIe Interface Host
- Connected with PCIe Interface Host for sending/receiving data
- Designing custom mining software (multi-threaded) in Python to communicate to mining pool with stratum protocol
- Optimized for throughput
- RTL Design of Keccak 800 (aka Odocrypt algorithm)
Designed to give you a hash at every single clock cycle running at 300MHz
- Tested on the BCU1525 Acceleration Development Kit
- Connected with PCIe Interface Host for sending/receiving data
- Designing custom mining software (multi-threaded) in Python to communicate to mining pool with stratum protocol
- Optimized for throughput
- RTL Design of Ethereum algorithm
Tested on FK33 board running at 400MHz
- Dag-Generation on FPGA
- Designed custom MAXI bus interface to communicate with HBM memory